The present invention relates to a semiconductor memory used in integrated memory circuits and integrated memory circuits for use with logic devices and more specifically to a ferroelectric random access memory and a chain type ferroelectric random access memory having memory cells of conventional architecture operated at low boost voltages, also to DRAM, a ferroelectric random access memory and a chain type ferroelectric random access having memory cells of conventional architecture operated by a negative word line method or a boosted sense ground method at low boost voltages.
The ferroelectric material has a hysteresis character in the relationship between applied electric field and induced polarization, wherein if the voltage applied across the electrodes of a ferroelectric thin film is returned to zero, some magnitude of polarization remains. Namely, the polarization generated when a voltage was applied is maintained even after the applied voltage has been removed. Another characteristic feature of this material is that if a certain magnitude of inverse voltage is applied, the direction of polarization is accordingly inverted in the ferroelectric material.
With focus on the above characteristics of the ferroelectric material, a ferroelectric random access memory has been developed that has an array of memory cells where the polarization in a ferroelectric thin film is stored as logical information.
There are two representative structures for ferroelectric random access memory cells: a structure in which a ferroelectric thin film is used as an insulative thin film inserted between the two electrodes of a capacitor that holds information; and the other structure in which a ferroelectric thin film is used as the gate insulative film in a MOS transistor used for switching operation.
The former structure is obtained by replacing the capacitor in the DRAM cell with a ferroelectric capacitor. Dipole charge of either two directions of polarity is taken out from the ferroelectric capacitor through a MOS transistor that serves as a transfer gate. Since this operation is a destructive readout, the read data is written back after readout.
The following are the basic structure, characteristics and principles in write/read operations of the former type of ferroelectric random access memory cells.
As types of ferroelectric random access memory cells, there are a 1T1C-type cell of which equivalent circuit is shown in FIG. 25A and a 2T2C-type cell comprising two 1T1C-type cells of which equivalent circuit is shown in FIG. 27A.
In the 1T1C-type cell shown in FIG. 25A, a MOS transistor Q as a transfer gate and a ferroelectric capacitor C serving as memory are electrically connected in series. A word line WL is electrically connected to the gate of the MOS transistor Q, a bit line BL to an electrode (drain) of the MOS transistor Q, and a plate line PL to an electrode (plate) of the capacitor C.
FIG. 25B is a hysteresis loop that explains how the 1T1C-type ferroelectric random access memory cell shown in FIG. 25A reads logical data “0” and “1”, indicating the relationship between a voltage (difference between the plate line voltage VPL and the bit line voltage VBL) applied to a ferroelectric thin film inserted between the electrodes of a ferroelectric capacitor and the magnitude of induced polarization P(C/m). The points “a” and “b” represent the magnitude of remnant polarization.
As hysteresis characteristics shown in FIG. 25B indicate, a cell can represent two different logical states by two residual polarization (Pr) points, “a” and “b”, which are the magnitudes of polarization observed when no voltage (V=0) is applied across the electrodes of the ferroelectric thin film in a ferroelectric capacitor.
Next, the principles of read/write operations in a 1T1C-type ferroelectric random access memory cell are explained with reference to the hysteresis loop shown in FIG. 25B.
First, the bit line voltage VBL is equalized to the ground voltage at the precharge cycle, and then the equalization is released. After the transistor Q is turned on and the word line WL is selected, the plate line voltage VPL is elevated from the ground voltage to the supply voltage to extract the charge stored in the capacitor C to the bit line. The resulting change in the bit line voltage is compared with the reference voltage generated from a cell for reference use and amplified by a sense amplifier (not shown).
When data “0” is read, the polarity in the capacitor C is not inverted and the amount of electric charge read out to the bit line is small. As a result of comparative amplification by the sense amplifier, the bit line (on the side of storage node in the capacitor C) voltage becomes equal to the ground voltage. Thus the polarization of the capacitor C moves from point “a” to point “c” on the hysteresis curve.
On the other hand, when data “1” is read, the polarity in the capacitor C is inverted and the amount of charge read out to the bit line when the supply power voltage is applied as the above plate line voltage VPL is larger than that in the operation of reading “0”. As a result of comparative amplification by the sense amplifier, the bit line (on the side of storage node in the capacitor C) voltage becomes equal to the supply power voltage. Thus the polarization in the capacitor C moves from point “b” to point “c” and then point “a” on the hysteresis curve.
Next, the data latched in the sense amplifier is sent to a data line (not shown) and the plate line voltage VPL is reduced to the ground voltage. Then, the polarization state moves back to point “a” when reading data “0” and moves to point “d” when reading data “1”.
Later, when the transistor Q is turned off, the polarization state moves from point “d” to point “b” when reading “1” and then the rewrite operation to the capacitor C is completed.
The above was an explanation of read/rewrite operations. When new data is written, the voltage equal to the supply power voltage should be applied to the bit line if data “1” is written, and the voltage equal to the ground voltage to an input/output line (not shown) if data “0” is written, while the supply power voltage is applied to the plate line.
In the 2T2C-type cell shown in FIG. 26A, a first bit line BL is electrically connected to an electrode of the first transistor Q1 in the first cell, and a second bit line /BL, paired with the first bit line BL, is electrically connected to an electrode of the second transistor Q2 in the second cell. The gates of two transistors Q1 and Q2 have a common word line WL, and the plate electrodes of the two capacitors C1 and C2 have a common plate line PL. The above two bit line BL and /BL are electrically connected to a sense amplifier (not shown) for amplifying the bit line sense voltage and an equalizer circuit (not shown), for example.
Next, the principles of read/write operations in the 2T2C-type ferroelectric random access memory cell are explained.
FIGS. 26A to 26D indicate the applied voltage and the state of polarization in the ferroelectric capacitor during write operation. FIGS. 27A to 27C indicate the applied voltage and the state of polarization in the ferroelectric capacitor during read operation.
FIG. 28 shows the voltage applied to the plate line during above data write and read operations. During write and read operations in the ferroelectric memory cell, the direction of polarization is controlled by changing the plate voltage PL in the selected memory cell as 0V→3V→0V, for example.
(A) In the case of writing data, the plate line voltage PL is set to 0V at first, and the voltages of the bit line pair BL and /BL are equalized to 0V. Now it is assumed that the two capacitors C1 and C2 have polarization of which directions are opposite to each other as shown in FIG. 26A.
First, the equalization of the bit lines is released. Next, as shown in FIG. 26B, 4.5V, for example, is applied to the word line WL and the two transistors Q1 and Q2 are turned on. Then 3V, for example, is applied to the plate line PL, and the charges in the capacitors C1 and C2 are read out to the bit line pair BL and /BL. At this moment, a voltage is induced across the electrodes of the capacitor C1 and its polarity is inverted but the polarity of the capacitor C2 is not inverted.
Next, as shown in FIG. 26C, 3V, for example, is applied to either of the bit lines BL or /BL (/BL, for example), and 0V to the rest (BL, for example), and then the plate line PL is returned to 0V as shown in FIG. 26D. As a result, a voltage is induced across the electrodes of the second capacitor C2 and its polarity is inverted but the polarity of the first capacitor C1 is not inverted. Thus polarization with polarity opposite to the initial direction has been written. Later, the word line WL is returned to 0V, and the two transistors Q1 and Q2 are returned to an off state.
(B) In the case of reading data, the plate line PL is set to 0V at first, and the bit line pair BL and /BL are equalized to 0V. It is assumed at this moment that two capacitors C1 and C2 have polarization of which directions are opposite to each other as shown in FIG. 27A.
First, the equalization of the bit lines is released. Next, as shown in FIG. 27B, 4.5V, for example, is applied to the word line WL and the two transistors Q1 and Q2 are turned on. Then 3V, for example, is applied to the plate line PL, and the charges in the capacitors C1 and C2 are read out to the bit line pair BL and /BL. At this moment, a voltage is induced across the electrodes of the second capacitor C2 and its polarity is inverted but the polarity of the first capacitor C1 is not inverted. As a result, the bit line voltage V(BL) becomes lower than the bit line voltage /V(BL). The voltages read from the two capacitors C1 and C2 are amplified by the sense amplifier, and the bit line voltage V(BL) and the bit line voltage N(BL) become 0V and 3V, respectively, as the output of the sense amplifier.
Then the plate line PL is returned to 0V as shown in FIG. 27C. As a result, a voltage is induced across the electrodes of the second capacitor C2 and its polarity is inverted again but the polarity of the first capacitor C1 is not inverted, returning to the initial state. Later, the word line WL is returned to 0V and the two transistors Q1 and Q2 are returned to an off state.
Such ferroelectric random access memory is under an intensive development effort these years because compared with other types of nonvolatile memory such as flash memory it allows a larger number of rewrites, takes shorter time for write operation, and operates at lower voltages with less power.
Such ferroelectric random access memory with those characteristics is expected to replace conventional memory such as DRAM, flash memory and SRAM. Also its integration with logic devices is raising great expectations. Furthermore, since the ferroelectric random access memory operates with no battery backup and at high speed, its use in non-contacting cards (RF-ID: Radio Frequency-Identification) has started.
On the other hand, if the bit line in the ferroelectric random access memory is made in a folded configuration, its line width cannot be made thinner than 8F2 (F is the minimum design line width). There is another problem that the operation speed of the ferroelectric random access memory is lower than that of DRAM because it drives the plate line containing a large capacity.
To solve those problems, the following papers have been presented to propose new architectures for chain FRAM: VLSI Circuit Sympo. 1997 p. 83–84 “High-Density Chain Ferroelectric Random Access Memory (CFRAM)”; and ISSCC Tech. Dig. Papers, pp. 102–103, February 1999 “A Sub-40 ns Random-Access Chain FRAM Architecture with 7 ns Cell-Plate-Line Drive”.
This type of ferroelectric random access memory has an array of memory cell units comprising two or more serially connected ferroelectric memory cells where the electrodes of the ferroelectric capacitor are electrically connected to the source and the drain of the MOS transistor. Any memory cell can be accessed as desired by turning on the transistors of non-selected cells and turning off the transistor of the selected cell.
According to those papers for chain type ferroelectric random access memory, a higher operation speed and a higher device density are provide, because its cell size becomes a half that of the conventional ferroelectric random access memory and its bit line width becomes ¼ that of the conventional ferroelectric random access memory. The following is a brief explanation of the conventional ferroelectric random access memory.
FIG. 29 is a schematic description of part of the conventional chain type ferroelectric random access memory electric circuit and in particular part of the memory cell array and part of the peripheral circuit.
In FIG. 29, memory cell units are arrayed in line in the memory cell area. In this memory cell unit, more than one memory cell is serially connected of which electrodes in the ferroelectric capacitor are electrically connected to the source and the drain of an enhanced-type (E-type) NMOS transistor.
The present example shows a representative memory cell unit comprising serially connected 8 memory cells, M0–M7 and BM0–BM7. The transistors in those cells, M0–M7, are denoted as Tr0–Tr7, the capacitors as C0–C7, and likewise the transistors in the cells BM0–BM7 are denoted as BTr0–BTr7, and the capacitors as BC0–BC7.
The gates of those transistors Tr0–Tr7 and BTr0–BTr7 are electrically connected to corresponding word lines WLr<0>–WLr<7>, and one electrode of the memory cell unit is electrically connected to the plate line PL<0> or PL<1>. The other electrode is electrically connected to the bit line BL or its complementary bit line BBL through a MOS transistor QB0 or QB1 that is used for selecting a block.
An equalizing circuit EQ, flip-flop-type sense amplifier SA and column selection gate CG are electrically connected to the above bit line pair BL and BBL.
The MOS transistors QB0 and QB2 that are used for selecting a block are controlled by the block select signals V(BSr<0>) and V(BSr<1>), the equalization circuit EQ is controlled by the equalization control signal V(BEQL), the sense amplifier SA is controlled by sense amplifier activation control signals V(SEN) and V(BSEP), and the column selection gate CG is controlled by the column select control signal V(CSL).
However, there is a typical problem in such structure shown in FIG. 29 that the stored polarization is reduced and a disturb takes place during conventional read/rewrite/write operations. This problem is discussed in detail as follows.
<First Example of Conventional Write Operation>
FIG. 30 shows a timing chart and a voltage waves figure has almost the same architecture the nodes BL1R–BL7R during operation in which the cells M0 and BM0 are selected by selecting a word line Wr<0>, for example, for a 2T2C-type cells shown in FIG. 29, data “0” is read from the cell M0 by the single plate pulse driving method, and then data “1” is written from outside the chip.
This first example of operation is explained in detail below with reference to FIG. 30.
First, the equalization control signal V(BEQL) is lowered to release the equalization of the pair of bit lines, and the word line control voltage V(WLr<0>) is lowered to select a word line WLr<0>. Next, the block select signals V(BSr<0>) and V(BSr<1>) are lifted to connect the memory cells M0 and BM0 to the bit line pair BL and BBL. Later, the plate line voltages V(PL<0>) and V(PL<1>) are lifted to read the charge of polarization in the memory cells M0 and BM0 out to the bit lines BL and BBL.
Then the sense amplifier activation signal V(SEN) is lifted and the sense amplifier activation signal V(BSEP) is lowered to activate the sense amplifier SA to perform comparative amplification. At this time since the polarization data stored in the memory cell M0 is “0”, namely, it has a direction from the plate line to the sense amplifier, as a result of the comparative amplification, the nodes BL1R-BL7R stand at the lifted plate line voltage but the node BL0R stands at 0V, as shown in FIG. 29.
Later, the column select signal V(CSL) is selected while the sense amplifier is activated, and data “1” is written from outside the chip through the column selection gate CG. Then if the elevated voltage in the word line is low, the nodes BL1R–BL7R are booted significantly. As a result voltages develop between:                Node BL7R and node BL6R;        Node BL6R and node BL5R;        Node BL5R and node BL4R;        Node BL4R and node BL3R;        Node BL3R and node BL2R;        Node BL2R and node BL1R.        
The reasons are shown below.
As described above, when the node voltage is further elevated by the sense amplifier SA than the lifted plate line voltage, the source voltages of the cell transfer gates Tr0–Tr7 rise and the voltage differences between the gates and the sources of the transfer gates Tr0–Tr7 grow. As a result, the transfer gates Tr0–Tr7 turn off because of a rise in their threshold level due to bias effects in the board. Since the node voltages are further booted by the sense amplifier SA after Tr0–Tr7 have been turned off, this voltage increment provided by the sense amplifier SA is shared by the capacity existing between the sense amplifier SA and the cell transfer gates Tr0–Tr7.
Consequently, voltage arises at both electrodes of each of the cell transfer gates Tr0–Tr7 and the level of polarization is lowered. In particular, between the node BL2R and the node BL1R, a large voltage bias appears. If the polarity of the memory cell M1 that has not been selected agrees with the direction form the plate line to the sense amplifier (namely, data is “0”), an electric field appears to reduce this accumulated polarization. This effect is called disturb.
<Second Example of Conventional Write Operation>
FIG. 31 consists of a timing chart and a voltage waves figure has almost the same architecture the nodes BL1R-BL7R during operations in which the cells M0 and BM0 are selected by selecting the word line Wr<0>, for example, for the 2T2C-type cells shown in FIG. 29, data “0” is read from the cell M0 by the double plate pulse driving method, and then data “1” is written from outside the chip.
This second examples of operation is explained in detail below with reference to FIG. 31.
First, the equalization control signal V(BEQL) is lowered to release the equalization of the pair of bit lines. The word line control voltage V(WLr<0>) is lowered to select a word line WLr<0>. Next, the block select signals V(BSr<0>) and V(BSr<1>) are lifted to connect the memory cells M0 and BM0 to the bit line pair BL and BBL.
Later, the plate line voltages V(PL<0>) and V(PL<1>) are lifted and lowered by pulses to read the charge of polarization in the memory cells M0 and BM0 out to the bit lines BL and BBL.
Then the sense amplifier activation signal V(SEN) is lifted and the sense amplifier activation signal V(BSEP) is lowered to activate the sense amplifier SA to perform comparative amplification. At this point in time, since the polarization data stored in the memory cell M0 is “0”, namely, it has a direction from the plate line to the sense amplifier, as a result of the comparative amplification, the nodes BL1R–BL7R stand at the lifted plate line voltage but the node BL0R stands at 0V, as shown in FIG. 31.
Later, the column select signal V(CSL) is selected while the sense amplifier is activated, and data “1” is written from outside the chip through the column selection gate CG. Then if the elevated voltage in the word line is low, the nodes BL1R–BL7R are booted significantly. As a result voltage differences appear between:                Node BL7R and node BL6R;        Node BL6R and node BL5R;        Node BL5R and node BL4R;        Node BL4R and node BL3R;        Node BL3R and node BL2R;        Node BL2R and node BL1R.        
The reasons are shown below.
As described above, when the node voltage is further elevated by the sense amplifier SA than the lifted plate line voltage, the source voltages of the cell transfer gates rise and the voltage differences between the gates and the sources of the transfer gates grow. As a result, the transfer gates Tr0–Tr7 turn off because of a rise in their threshold level due to bias effects in the board. Since the node voltages are further booted by the sense amplifier SA after Tr0–Tr7 have been turned off, this voltage increment provided by the sense amplifier SA is shared by the capacity existing between the sense amplifier SA and the cell transfer gates Tr0–Tr7.
Consequently, voltage arises at both electrodes of each of the cell transfer gates Tr0–Tr7 and the level of polarization is lowered. In particular, between the node BL2R and the node BL1R, a large voltage bias appears. If the polarity of the memory cell M1 that has not been selected agrees with the direction form the plate line to the sense amplifier (namely, data is “0”), an electric field appears to reduce this accumulated polarization. This effect is called disturb.
<Third Example of Conventional Write Operation>
FIG. 32 shows a timing chart and a voltage waves figure has almost the same architecture the nodes BL1R–BL7R during operation in which the cells BM7 and M7 are selected by selecting a word line Wr<7>, for example, for the 2T2C-type cells shown in FIG. 29, data “1” is read from the cell M7 by the double plate pulse driving method.
This third examples of operation is explained in detail below with reference to FIG. 32.
First, the equalization control signal V(BEQL) is lowered to release the equalization of the pair of bit lines. The word line control voltage V(WLr<7>) is lowered to select a word line WLr<7> is selected. Next, the block select signals V(BSr<0>) and V(BSr<1>) are lifted to connect the memory cells BM7 and M7 to the bit line pair BL and BBL.
Later, the plate line voltages V(PL<0>) and V(PL<1>) are lifted to read the charge of polarization in the memory cells BM7 and M7 out to the bit lines BL and BBL.
Then the sense amplifier activation signal V(SEN) is lifted and the sense amplifier activation signal V(BSEP) is lowered to activate the sense amplifier SA to perform comparative amplification. At this time since the polarization data stored in the memory cell BM7 is “1”, namely, it has a direction from the sense amplifier to the plate line, the nodes BBL0R–BBL7R are booted significantly when the plate line voltages V(PL<0>) and V(PL<1>) are changed from “L” to “H” if the elevated voltage in the word line is low. As a result voltage differences appear between:                Node BBL7R and node BBL6R;        Node BBL6R and node BBL5R;        Node BBL5R and node BBL4R;        Node BBL4R and node BBL3R;        Node BBL3R and node BBL2R;        Node BBL2R and node BBL1R.        
The reasons are shown below.
If the elevated voltage in the word line is low and the threshold level of the transfer gates BTr0–BTr7 is high, when the node voltage is booted by the plate line to a value higher than the supply power voltage of the sense amplifier SA, the source voltage of each cell transfer gate rises and the voltage differences between the gates and the sources of the transfer gates BTr0–BTr7 grow. As a result, the transfer gates BTr0–BTr7 turn off because of a rise in their threshold level due to bias effects in the board. Since the node voltages are further booted by the sense amplifier SA after BTr0–BTr7 have been turned off, this voltage increment provided by the sense amplifier SA is shared by the capacity existing between the plate line and the cell transfer gates BTr0–BTr7.
Consequently, between the node BBL7R and the node BBL6R in particular, a large voltage bias appears. If the polarity of the memory cell BM6 that has not been selected agrees with the direction form the sense amplifier to the plate line (namely, data is “1”), an electric field appears to reduce the accumulated polarization. This effect is called disturb.
The above explanations were made for the case in which the bit line was precharged to 0V during data read. However, in the first and second examples of operation, disturb also takes place even when the bit line is precharged to a high level during data read.
To date, the above problem itself with regard to disturb in the conventional chain type ferroelectric random access memory has not been pointed out or no solution has been presented.
Moreover, there is another problem in FRAN of the conventional memory cell structure that when data is read by the single plate pulse driving method, the plate voltage is significantly booted and the reliability of the cell capacitor is undermined. The reasons are shown below.
FIG. 33 is a schematic description of part of a ferroelectric random access memory having the conventional memory cell architecture and in particular part of the memory cell array and part of the peripheral circuit.
In FIG. 33, memory cells are arrayed in lines in the memory cell area. In this example, two memory cells M0 and BM0 are taken as examples, the transistors in these cells are denoted as Tr0 and BTr0, and the capacitors as C0 and BC0. One of the electrodes of each capacitor C0 and BC0 is electrically connected to the plate lines PL<0> and PL<B0>, respectively; the gates of the transistors Tr0 and BTR0 are electrically connected to the word lines WL<0> and WL<B0>; and one of the electrodes of the transistors Tr0 and BTr0 is electrically connected to the bit line BL and its complementary bit line BBL, respectively.
An equalizing circuit EQ, flip-flop-type sense amplifier SA and column selection gate CG are electrically connected to the above bit line pair BL and BBL.
The equalization circuit EQ is controlled by the equalization control signals V(BEQL), the sense amplifier SA is controlled by the sense amplifier activation control signals V(SEN) and V(BSEP), and the column selection gate CG is controlled by the column selection control signal V(CSL).
FIG. 34 is a timing chart indicating an operation in which the word lines WL<0> and WL<B0> in the ferroelectric random access memory shown in FIG. 33 are selected to select the cells M and BM0, and data “1” is read from the cell M0 by the single plate pulse driving method.
The above operation is explained in detail with reference to FIG. 34. It is assumed that the cell M0 has a polarity directing from the bit line to the plate line (data “1”) and the cell BM0 has a polarity directing from the plate line to the bit line (data “0”).
First, the equalization of the bit lines BL and BBL is released by reducing the equalization control signal V(BEQL) to be ready to read data out to the bit lines BL and BBL. Next, the word lines WL<0> and WL<B0> are selected by elevating the word line voltages V(WL<0>) and V(WL<B0>) from 0V to VPP. Then the charges of polarization in the memory cells M0 and BM0 are read out to the bit line pair, BL and BBL, by lifting the plate line voltage V(PL<0>) and V(PL<B0>) from 0V to V(PLPW).
At the next step, the sense amplifier activation signal V(SEN) is raised and the sense amplifier signal V(BSEP) is lowered to activate the sense amplifier SA and perform sense amplification. Data is read out from the chip by raising the column select signal V(CSL) to turn on the column selection gate CG.
Since the above sense amplification is conducted when the plate line voltages V(PL<0>) and V(PL<B0>) are raised to V(PLPW), the plate line voltage V(PL<0>) is booted up to a voltage higher than V(PLPW) because of a coupling of the bit line BL and the plate line PL<0> when data “1” stored in the cell M0 is read out.
Later, the plate line voltages V(PL<0>) and V(PL<B0>) are lowered to 0V and the word line voltages V(WL<0>) and V(WL<B0>) are also lowered from VPP to 0V to make the word lines WL<0> and WL<B0> non-selected. Finally, the sense amplifier activation signal V(SEN) is lowered and the sense amplifier signal V(BSEP) is raised to deactivate the sense amplifier SA.
As pointed out before, there is a problem that when the plate voltage is significantly booted by a coupling of the bit line BL and the plate line PL<0>, the reliability of the cell capacitor is affected.
On the other hand, as the supply power voltage for semiconductor memory has been lowered, its operation speed is also lowered unless the threshold value of MOS transistor is lowered in proportion. However, since information is stored in a form of electric charge in a capacitor in the memory cell in DRAM, the threshold in the transfer gate cannot be reduced. As a result, the minimum value of the threshold is left around 0.7V.
Because the threshold in MOS transistor cannot be lowered, the following two problems occur:
(1) If MOS transistor is made smaller, its threshold value remains high. Then charge density in the board becomes extremely high, resulting in an increase in the electric field at the junction, an increase in leakage current at the junction and a decline in the refresh characteristics;
(2) Since the voltage difference between the word line voltage VWL and the bit line voltage VBL cannot be enhanced enough to turn on the cell transfer gate, a high voltage boost rate (VWL/VBL) is required. Consequently, the design of the booster circuit becomes complicated.
Then the following two proposals have allowed DRAM to reduce the threshold value of MOS transistor. Those technologies aim at reducing current leakage at the transfer gate even under a low threshold value.
(1) Negative Word Line (NWL) method
FIG. 35A and FIG. 35B indicate a schematic configuration of a DRAM employing the NWL method and the relationship between the word line WL and the high level voltage VBL(H) and the low-level voltage VBL(L) of the bit lines BL and /BL.
In FIG. 35A, Q is the cell transfer gate, C the cell capacitor, WL the word line, WLD the word line driver, BL and /BL the bit line pair, SA the sense amplifier, and SDA the sense amplifier driver.
In this method, the low level “L” of voltage amplified by the sense amplifier SA, namely, the bit line voltage VBL(L), is set to the ground voltage VSS, and the voltage “L” of the word line WL is set to the negative voltage VBB. Then a negative bias VBB is applied between the gate and the source of the cell transfer gate Q and the cut-off characteristics of the transfer gate Q are improved.
Note that the high level “H” of the word line WL has been booted to a value higher than the high level “H” of the output of the sense amplifier SA, namely, the bit line voltage VBL(H), by an amount of the threshold value Vth3 of the cell transfer gate Q plus a (namely, at least Vth3).
(2) Boosted Sense Ground (BSG) Method
FIG. 36A and FIG. 36B indicate a schematic configuration of a DRAM employing the BSG method and the relationship between the word line WL and the high level voltage VBL(H) and the low-level voltage VBL(L) of the bit lines BL and /BL.
In FIG. 36A, Q is the cell transfer gate, C the cell capacitor, WL the word line, WLD the word line driver, BL and /BL the bit line pair, SA the sense amplifier, SDA the sense amplifier driver, and VOFF the off-set voltage.
In this method, the low level “L” of voltage amplified by the sense amplifier SA, namely, the bit line voltage VBL(L), is set to a value higher by VOFF than the ground voltage VSS. Since a negative bias VOFF is applied between the gate and the source of the cell transfer gate Q, the cut-off characteristics of the transfer gate Q are improved.
Note that the high level “H” of the word line WL has been booted to a value higher than the high level “H” of the output of the sense amplifier SA, namely, the bit line voltage VBL(H), by an amount of the threshold value Vth2 of the cell transfer gate Q plus α (namely, at least Vth2).
As mentioned above, those methods have been proposed to meet requirements for lower power consumption and lower voltage in DRAM. However, as long as a positive value is used as the threshold value of the cell transfer gate, a value of VPP higher than the supply power voltage VCC plus Vth (the threshold value of the cell transfer gate) is required as the boot voltage for the word line. The same holds true for conventional ferroelectric random access memory.
As pointed out above, there is a problem in the conventional ferroelectric random access memory that disturb is induced during read/write operations and that the accumulated polarization is attenuated.
There is another problem in FRAN of the conventional memory cell structure that when data is read by the single plate pulse driving method, the plate voltage is significantly booted and the reliability of the cell capacitor is affected.
Another problem in DRAM and ferroelectric random access memory of the conventional memory cell structure is that a booster circuit is necessary to provide a word line voltage higher than the supply voltage plus the threshold value of the cell transfer gate because they use a positive value for the threshold of the cell transfer gate in both cases of the NWL and BSG methods.